1. Field of the Invention
The present invention generally relates to a repair circuit of a semiconductor memory device, and more particularly, to a repair circuit of a semiconductor memory device, in which it can prevent a repair cell from operating slower than a normal memory cell.
2. Discussion of Related Art
A semiconductor memory device does not function as a memory device if even one of many delicate cells fails. To discard the whole device as a failed product despite the fact that only several cells within the memory have failed, however, is inefficient in terms of the yield.
Currently, the memory device is restored by replacing a failed normal unit cell with a reservation unit cell that is previously provided in the memory device in order to improve the yield.
FIG. 1 is a block diagram illustrating the process of performing the repair operation in the related art. FIG. 2 is a timing diagram of signals illustrating the address generating operation in the related art. The address generating process and the repair operation principle of the NAND flash memory device in the related art will be described below with reference to FIGS. 1 and 2.
(1) Address Generating Process of NAND Flash Memory Device
The NAND flash memory device does not include address pins since the I/O of data is performed serially. Furthermore, addresses are generated by a write enable signal WE# or a read enable signal RE#.
An address start signal is first input through an ALE (Address Latch Enable) pin and the I/O. The ALE pin is a pin for address input. The write enable signal WE# is input to an address counter. The address counter increases the address whenever the write enable signal WE# is toggled. The address counter also increases the internal address by detecting the rising edge of the write enable signal WE# within the chip. When it is sought to output data, the address is increased in the same manner as above using the read enable signal RE#.
If the write enable signal WE# or the read enable signal RE# is input to the input terminal, the address counter increases the address.
The increased address COLADD or ROWADD must be transferred to a cell operation block (a repair controller,) within the chip. Eventually, a column address signal COLADDC[j] is generated by an address counter when a write enable signal WE# or a read enable signal being inputted through an input terminal is inputted to the address counter. It takes a time Tadd for the column address signal to reach the cell operation block (a repair controller). As a result, the time taken for a repair address signal RADD to reach the repair scramble unit is longer than is the time taken for a column address signal COLADD[j] to reach the address scramble by the time taken for the repair address signal RADD generated in the repair controller to reach the repair scramble. This causes the operating speed of the repair cell to be later than that of the normal memory cell.
(2) Repair Operation
In the normal memory cell or the repair cell, input or output of the data is performed according to the address change. However, to perform the repair operation, addresses to be repaired must be compared and I/O to be repaired must be set. This operation is performed by the repair controller.
If a new address is input when data are output, the data I/O operation is performed by the page buffer in the case of a general cell. In the case of a repair cell, however, the I/O operation is performed according to control signals (a signal RIO to indicate I/O to be repaired, an address RADD to indicate a repair column), which are generated by the repair controller.
Therefore, the operation of the repair cell becomes later than the operation of the general cell by a time during which the repair controller is activated and is transmitted to the repair scramble. As a result, the operating speed of the repair cell defines the operating speed of the chip.
There is a limit to a reduction of a time which is taken for the repair controller to operate. If the spec defining the data I/O time is reduced, the desirable spec of the device cannot be obtained due to the operating time of the repair controller.
For example, in the case of a 512 Mb NAND flash memory, the time taken to input and output one byte is 50 ns. In the case of a 2 Gb NAND flash memory, the time taken to input and output one byte is 30 ns, and in the case of 4 Gb, 25 ns. However, in the 512 Mb, 2 Gb, and 4 Gb, the operating time of the repair controller is the same or longer. Therefore, they do not satisfy the spec of the device for the I/O time.